Intel to Meta
The patents describe advanced processor architectures featuring multiple cores with distinct processing architectures, employing a sophisticated cache hierarchy to maintain coherence between different functional circuits, including graphics devices. Key innovations include a communication interconnect that facilitates seamless information sharing without needing to access main memory, and caching strategies that enable power control and efficient resource management. These technologies have potential applications in high-performance computing, graphics processing, and energy-efficient system designs.
Breadth Distribution
Complexity Distribution
Enforceability Distribution
Infringement Distribution
Patents
| Patent Number | Summary | Breadth | Complexity | Enforceability | Infringement |
|---|---|---|---|---|---|
| 10204051 | The patent describes a system featuring multiple cores with a first processing architecture, a hierarchical cache structure and cache coherence circuitry that enables efficient communication and coherence between these cores and functional circuits of a second processing architecture, thereby facilitating tasks such as graphics processing, memory control, and digital signal processing across separate dies. |
B
|
C
|
C
|
- |
| 10078590 | This patent protects a multi-core processor architecture featuring a hierarchical cache system with integrated cache coherence mechanisms, enabling seamless data sharing and communication between processor cores and various functional circuits, including graphics processing, while ensuring data integrity through snoop operations. |
A
|
D
|
C
|
- |
| 09946650 | The patent protects a multi-processor system incorporating a cache hierarchy and cache coherence circuitry that allows for efficient information sharing between processing cores and functional circuits with differing architectures, facilitating operations such as graphics and memory control while ensuring coherence through snoop operations. |
A
|
D
|
C
|
- |
| 09665488 | This patent protects an apparatus integrating a central processing unit and a graphics processing unit with distinct cache coherency domains, enabling the latter to access an L2 cache directly for improved information sharing and operational efficiency, while maintaining coherency between both processing units. |
A
|
C
|
B
|
- |
| 09128698 | This patent protects a method and apparatus for executing a combined rotate and XOR instruction in a computer processor, wherein the execution can alternate between two operational modes based on an immediate value, facilitating efficient computational tasks such as those used in hashing algorithms like Skein and Blake. |
C
|
C
|
C
|
- |
| 09035960 | This patent protects an apparatus and method for enabling information sharing between a processor and a first coherency domain featuring multiple cache hierarchies while allowing specific snooping capabilities, which enhances data access efficiency without necessitating main memory access. |
C
|
D
|
C
|
- |
| 09035962 | The patent protects a system comprising a CPU and a graphics device with distinct cache coherency rules, enabling efficient data sharing between their respective cache hierarchies through a mid-level cache that applies the respective rules for coherence. |
C
|
C
|
C
|
- |
| 09035959 | This patent protects an innovative microprocessor architecture that includes distinct CPU and GPU cache coherency domains with hierarchically organized caches (L1, MLC, LLC) enabling efficient data access and sharing between the CPU and GPU without directly accessing system memory. |
C
|
C
|
C
|
- |
| 08713256 | This patent protects a method and apparatus for dynamically managing power and cache availability in a multi-core processor system by monitoring and adjusting the last level cache (LLC) usage, thereby optimizing power consumption based on real-time cache demand and processor activity. |
B
|
C
|
B
|
- |
| 08643660 | This patent protects a processor architecture that includes two central processing units (CPUs) and a non-CPU functional unit, such as a graphics processing unit (GPU), with interconnect logic allowing direct information sharing among these units through dedicated caches that cannot be snooped by the CPUs, optimizing access and performance without relying on main memory. |
C
|
B
|
C
|
- |
Patent Details
10204051
- Technique to share information among different cache coherency domains
Published: 2019-02-12
The patent describes a system featuring multiple cores with a first processing architecture, a hierarchical cache structure and cache coherence circuitry that enables efficient communication and coherence between these cores and functional circuits of a second processing architecture, thereby facilitating tasks such as graphics processing, memory control, and digital signal processing across separate dies.
B
Breadth
C
Complexity
C
Enforceability
Claims
Infringement Analysis
10078590
- Technique to share information among different cache coherency domains
Published: 2018-09-18
This patent protects a multi-core processor architecture featuring a hierarchical cache system with integrated cache coherence mechanisms, enabling seamless data sharing and communication between processor cores and various functional circuits, including graphics processing, while ensuring data integrity through snoop operations.
A
Breadth
D
Complexity
C
Enforceability
Claims
Infringement Analysis
09946650
- Technique to share information among different cache coherency domains
Published: 2018-04-17
The patent protects a multi-processor system incorporating a cache hierarchy and cache coherence circuitry that allows for efficient information sharing between processing cores and functional circuits with differing architectures, facilitating operations such as graphics and memory control while ensuring coherence through snoop operations.
A
Breadth
D
Complexity
C
Enforceability
Claims
Infringement Analysis
09665488
- Technique to share information among different cache coherency domains
Published: 2017-05-30
This patent protects an apparatus integrating a central processing unit and a graphics processing unit with distinct cache coherency domains, enabling the latter to access an L2 cache directly for improved information sharing and operational efficiency, while maintaining coherency between both processing units.
A
Breadth
C
Complexity
B
Enforceability
Claims
Infringement Analysis
09128698
- Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction
Published: 2015-09-08
This patent protects a method and apparatus for executing a combined rotate and XOR instruction in a computer processor, wherein the execution can alternate between two operational modes based on an immediate value, facilitating efficient computational tasks such as those used in hashing algorithms like Skein and Blake.
C
Breadth
C
Complexity
C
Enforceability
Claims
Infringement Analysis
09035960
- Technique to share information among different cache coherency domains
Published: 2015-05-19
This patent protects an apparatus and method for enabling information sharing between a processor and a first coherency domain featuring multiple cache hierarchies while allowing specific snooping capabilities, which enhances data access efficiency without necessitating main memory access.
C
Breadth
D
Complexity
C
Enforceability
Claims
Infringement Analysis
09035962
- Technique to share information among different cache coherency domains
Published: 2015-05-19
The patent protects a system comprising a CPU and a graphics device with distinct cache coherency rules, enabling efficient data sharing between their respective cache hierarchies through a mid-level cache that applies the respective rules for coherence.
C
Breadth
C
Complexity
C
Enforceability
Claims
Infringement Analysis
09035959
- Technique to share information among different cache coherency domains
Published: 2015-05-19
This patent protects an innovative microprocessor architecture that includes distinct CPU and GPU cache coherency domains with hierarchically organized caches (L1, MLC, LLC) enabling efficient data access and sharing between the CPU and GPU without directly accessing system memory.
C
Breadth
C
Complexity
C
Enforceability
Claims
Infringement Analysis
08713256
- Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance
Published: 2014-04-29
This patent protects a method and apparatus for dynamically managing power and cache availability in a multi-core processor system by monitoring and adjusting the last level cache (LLC) usage, thereby optimizing power consumption based on real-time cache demand and processor activity.
B
Breadth
C
Complexity
B
Enforceability
Claims
Infringement Analysis
08643660
- Technique to share information among different cache coherency domains
Published: 2014-02-04
This patent protects a processor architecture that includes two central processing units (CPUs) and a non-CPU functional unit, such as a graphics processing unit (GPU), with interconnect logic allowing direct information sharing among these units through dedicated caches that cannot be snooped by the CPUs, optimizing access and performance without relying on main memory.
C
Breadth
B
Complexity
C
Enforceability
Claims
Infringement Analysis