Intel to Altera
This patent portfolio encompasses innovations in electronic device interconnects, particularly through the integration of clock and data recovery circuitry, phase adjustment, and programmable logic within semiconductor devices and integrated circuits. Notably, advancements in data migration techniques for server register states and enhanced processing capabilities in server and virtual integrated circuits showcase significant improvements in efficiency and adaptability. The inclusion of programmable interconnections and optical communication links further enhances the data transmission efficiency and flexibility in heterogeneous circuit architectures.
Breadth Distribution
Complexity Distribution
Enforceability Distribution
Infringement Distribution
Patents
| Patent Number | Summary | Breadth | Complexity | Enforceability | Infringement |
|---|---|---|---|---|---|
| 12055777 | A dual integrated circuit system featuring optical engines for high-speed data communication between packages over optical links. |
B
|
C
|
C
|
- |
| 11995028 | An electronic device featuring a high-bandwidth memory (HBM) paired with an integrated circuit that integrates programmable logic, memory controllers, and dual hierarchical Network-on-Chip (NOC) architectures to facilitate high-speed data routing between memory and processors. |
B
|
D
|
C
|
- |
| 11804844 | The method allows for the rapid migration of a virtual integrated circuit between personas on different integrated circuitry without perceptible interruption to the user. |
A
|
C
|
C
|
- |
| 11726545 | A server with distinct register states for non-critical and critical operations, which enables the extraction and migration of critical register states to a destination server while maintaining the integrity of non-critical states. |
B
|
B
|
B
|
- |
| 11580054 | A programmable logic device featuring integrated Network-on-Chip (NoC) routers that enable efficient data transmission between data processing cores and memory devices, with configurable bypass modes and crossbar circuitry to optimize connectivity and performance. |
A
|
C
|
B
|
- |
| 11356303 | An electronic device featuring an interconnect with multiple lanes that facilitate high-speed data transmission and clock synchronization between two semiconductor devices through integrated clock and data recovery circuits, equalizers, and phase adjustment circuitry. |
C
|
D
|
C
|
- |
| 11327259 | An integrated circuit package featuring multiple dies that integrate processing circuitry, a transceiver, and an optical engine to facilitate direct analog signal transmission for optical communication. |
C
|
C
|
C
|
- |
| 10965501 | An electronic device featuring an interconnect with multiple lanes that include clock and data recovery circuitry for signal processing and phase adjustment, enabling efficient data transmission between two semiconductor devices. |
C
|
D
|
B
|
- |
| 10530614 | An electronic device utilizing an interconnect with multiple lanes that include clock and data recovery circuitry and phase adjustment and clock multiplier circuits to facilitate signal transmission and synchronization between two semiconductor devices. |
C
|
C
|
B
|
- |
| 08735857 | A semiconductor device featuring serially connected P-type and N-type transistors with configurable interconnections using programmable vias, allowing for flexible circuit configurations without hardwired connections between transistor gates. |
C
|
C
|
B
|
- |
| 08477773 | A method for classifying data packets in a network by inspecting header fields and utilizing an extended ternary content addressable memory (ETCAM) to achieve multi-dimensional classification through address space compression. |
B
|
D
|
C
|
- |
Patent Details
12055777
- Integrated circuit package with electro-optical interconnect circuitry
Published: 2024-08-06
A dual integrated circuit system featuring optical engines for high-speed data communication between packages over optical links.
B
Breadth
C
Complexity
C
Enforceability
Claims
Infringement Analysis
11995028
- Scalable network-on-chip for high-bandwidth memory
Published: 2024-05-28
An electronic device featuring a high-bandwidth memory (HBM) paired with an integrated circuit that integrates programmable logic, memory controllers, and dual hierarchical Network-on-Chip (NOC) architectures to facilitate high-speed data routing between memory and processors.
B
Breadth
D
Complexity
C
Enforceability
Claims
Infringement Analysis
11804844
- Programmable logic device virtualization
Published: 2023-10-31
The method allows for the rapid migration of a virtual integrated circuit between personas on different integrated circuitry without perceptible interruption to the user.
A
Breadth
C
Complexity
C
Enforceability
Claims
Infringement Analysis
11726545
- Methods and apparatus for selectively extracting and loading register states
Published: 2023-08-15
A server with distinct register states for non-critical and critical operations, which enables the extraction and migration of critical register states to a destination server while maintaining the integrity of non-critical states.
B
Breadth
B
Complexity
B
Enforceability
Claims
Infringement Analysis
11580054
- Scalable network-on-chip for high-bandwidth memory
Published: 2023-02-14
A programmable logic device featuring integrated Network-on-Chip (NoC) routers that enable efficient data transmission between data processing cores and memory devices, with configurable bypass modes and crossbar circuitry to optimize connectivity and performance.
A
Breadth
C
Complexity
B
Enforceability
Claims
Infringement Analysis
11356303
- Short link efficient interconnect circuitry
Published: 2022-06-07
An electronic device featuring an interconnect with multiple lanes that facilitate high-speed data transmission and clock synchronization between two semiconductor devices through integrated clock and data recovery circuits, equalizers, and phase adjustment circuitry.
C
Breadth
D
Complexity
C
Enforceability
Claims
Infringement Analysis
11327259
- Integrated circuit package with electro-optical interconnect circuitry
Published: 2022-05-10
An integrated circuit package featuring multiple dies that integrate processing circuitry, a transceiver, and an optical engine to facilitate direct analog signal transmission for optical communication.
C
Breadth
C
Complexity
C
Enforceability
Claims
Infringement Analysis
10965501
- Short link efficient interconnect circuitry
Published: 2021-03-30
An electronic device featuring an interconnect with multiple lanes that include clock and data recovery circuitry for signal processing and phase adjustment, enabling efficient data transmission between two semiconductor devices.
C
Breadth
D
Complexity
B
Enforceability
Claims
Infringement Analysis
10530614
- Short link efficient interconnect circuitry
Published: 2020-01-07
An electronic device utilizing an interconnect with multiple lanes that include clock and data recovery circuitry and phase adjustment and clock multiplier circuits to facilitate signal transmission and synchronization between two semiconductor devices.
C
Breadth
C
Complexity
B
Enforceability
Claims
Infringement Analysis
08735857
- Via-configurable high-performance logic block architecture
Published: 2014-05-27
A semiconductor device featuring serially connected P-type and N-type transistors with configurable interconnections using programmable vias, allowing for flexible circuit configurations without hardwired connections between transistor gates.
C
Breadth
C
Complexity
B
Enforceability
Claims
Infringement Analysis
08477773
- Method, device and system for multi field classification in a data communications network
Published: 2013-07-02
A method for classifying data packets in a network by inspecting header fields and utilizing an extended ternary content addressable memory (ETCAM) to achieve multi-dimensional classification through address space compression.
B
Breadth
D
Complexity
C
Enforceability
Claims
Infringement Analysis