AMD to Onesta IP
This patent portfolio introduces several innovations in computing systems, including a GPU chiplet architecture for enhanced inter-chiplet communication, advanced texture compression techniques with variable partitioning, and improved memory allocation methods for multi-processor environments. Key contributions also include redundancy in shader arrays to enhance rendering reliability and load balancing in neural network execution through metadata tagging. These technologies have potential applications in high-performance gaming, AI processing, and efficient memory management in complex computing systems.
Breadth Distribution
Complexity Distribution
Enforceability Distribution
Infringement Distribution
Patents
| Patent Number | Summary | Breadth | Complexity | Enforceability | Infringement |
|---|---|---|---|---|---|
| 12032965 | This patent protects a processor and method for dynamically throttling the execution of threads based on a comparison of cache misses to a threshold, allowing for adjusted instruction processing rates to improve overall resource efficiency and manage cache contention. |
C
|
C
|
C
|
- |
| 11948223 | This patent protects a system and method for enhancing the reliability of a shader pipe array by incorporating a redundant shader pipe array, horizontal data transfer paths, and control circuitry to automatically reroute processing tasks to functional shader pipes when defects are detected in the shader pipe array. |
C
|
C
|
C
|
- |
| 11880715 | This patent introduces a method and system for load balancing in a neural network that leverages tagged metadata to improve computational efficiency by detecting available resources and performing load balancing for neuron execution across layers, while incorporating factors such as neuron readiness and computational costs. |
C
|
B
|
C
|
- |
| 11841803 | This patent protects a GPU chiplet array system that features a central processing unit (CPU) coupled to multiple GPU chiplets via a dedicated passive crosslink for efficient inter-chiplet communication and cache utilization, enhancing data access and processing performance. |
C
|
D
|
C
|
- |
| 11741019 | This patent protects a method and system for dynamic memory allocation in a multi-processor computer architecture, allowing for the mapping of memory operations from processors to designated virtual memory pools associated with specific memory resources, which can vary in accessibility based on the originating processor and architectural requirements. |
C
|
B
|
C
|
- |
| 11386520 | Patent 11386520 protects a redundant shader piping system designed to enhance rendering performance by identifying defective shader pipes and facilitating the real-time transfer of processed data to a redundant shader pipe array, thereby minimizing rendering disruptions and optimizing data management through a combination of direct paths, delay buffers, and selective data transfer. |
C
|
D
|
C
|
- |
| 11169812 | This patent protects an apparatus and method for managing instruction processing in a computing environment by dynamically throttling instruction execution based on a computed threshold of cache misses for individual threads, thereby optimizing performance and resource utilization. |
B
|
C
|
C
|
- |
| 11119944 | This patent protects a method and system for efficiently allocating memory in a multi-processor computer system by mapping memory operations to virtual memory pools based on the originating processor, thereby optimizing access to shared memory resources. |
B
|
B
|
C
|
- |
| 10970120 | This patent protects a method and system for load balancing in a neural network by utilizing metadata to tag kernels, neurons, and layers with information about their availability and readiness, enabling dynamic scheduling of computations in subsequent layers while the current layer is processed. |
B
|
C
|
C
|
- |
| 10861122 | This patent protects a system for rendering calculations that includes a shader pipe array with redundancy features, enabling the identification of defective shader pipes and the independent rerouting of data to a redundant shader pipe array through horizontal paths, ensuring uninterrupted rendering performance. |
C
|
B
|
C
|
- |
| 10324860 | The patent describes a method and system for managing memory allocation in a multi-processor environment by mapping shared memory addresses to multiple virtual memory pools, thereby allowing fine control over accessibility and resource management for each processor. |
C
|
B
|
C
|
- |
| 10205956 | This patent protects a method and system for texture compression that involves variable partitioning of pixels into subsets, selective compression based on quality thresholds, and techniques such as palletization and color ramp definitions, enabling efficient storage and representation of textures. |
B
|
C
|
C
|
- |
Patent Details
12032965
- Throttling while managing upstream resources
Published: 2024-07-09
This patent protects a processor and method for dynamically throttling the execution of threads based on a comparison of cache misses to a threshold, allowing for adjusted instruction processing rates to improve overall resource efficiency and manage cache contention.
C
Breadth
C
Complexity
C
Enforceability
Claims
Infringement Analysis
11948223
- Redundancy method and apparatus for shader column repair
Published: 2024-04-02
This patent protects a system and method for enhancing the reliability of a shader pipe array by incorporating a redundant shader pipe array, horizontal data transfer paths, and control circuitry to automatically reroute processing tasks to functional shader pipes when defects are detected in the shader pipe array.
C
Breadth
C
Complexity
C
Enforceability
Claims
Infringement Analysis
11880715
- Method and system for opportunistic load balancing in neural networks using metadata
Published: 2024-01-23
This patent introduces a method and system for load balancing in a neural network that leverages tagged metadata to improve computational efficiency by detecting available resources and performing load balancing for neuron execution across layers, while incorporating factors such as neuron readiness and computational costs.
C
Breadth
B
Complexity
C
Enforceability
Claims
Infringement Analysis
11841803
- GPU chiplets using high bandwidth crosslinks
Published: 2023-12-12
This patent protects a GPU chiplet array system that features a central processing unit (CPU) coupled to multiple GPU chiplets via a dedicated passive crosslink for efficient inter-chiplet communication and cache utilization, enhancing data access and processing performance.
C
Breadth
D
Complexity
C
Enforceability
Claims
Infringement Analysis
11741019
- Memory pools in a memory model for a unified computing system
Published: 2023-08-29
This patent protects a method and system for dynamic memory allocation in a multi-processor computer architecture, allowing for the mapping of memory operations from processors to designated virtual memory pools associated with specific memory resources, which can vary in accessibility based on the originating processor and architectural requirements.
C
Breadth
B
Complexity
C
Enforceability
Claims
Infringement Analysis
11386520
- Redundancy method and apparatus for shader column repair
Published: 2022-07-12
Patent 11386520 protects a redundant shader piping system designed to enhance rendering performance by identifying defective shader pipes and facilitating the real-time transfer of processed data to a redundant shader pipe array, thereby minimizing rendering disruptions and optimizing data management through a combination of direct paths, delay buffers, and selective data transfer.
C
Breadth
D
Complexity
C
Enforceability
Claims
Infringement Analysis
11169812
- Throttling while managing upstream resources
Published: 2021-11-09
This patent protects an apparatus and method for managing instruction processing in a computing environment by dynamically throttling instruction execution based on a computed threshold of cache misses for individual threads, thereby optimizing performance and resource utilization.
B
Breadth
C
Complexity
C
Enforceability
Claims
Infringement Analysis
11119944
- Memory pools in a memory model for a unified computing system
Published: 2021-09-14
This patent protects a method and system for efficiently allocating memory in a multi-processor computer system by mapping memory operations to virtual memory pools based on the originating processor, thereby optimizing access to shared memory resources.
B
Breadth
B
Complexity
C
Enforceability
Claims
Infringement Analysis
10970120
- Method and system for opportunistic load balancing in neural networks using metadata
Published: 2021-04-06
This patent protects a method and system for load balancing in a neural network by utilizing metadata to tag kernels, neurons, and layers with information about their availability and readiness, enabling dynamic scheduling of computations in subsequent layers while the current layer is processed.
B
Breadth
C
Complexity
C
Enforceability
Claims
Infringement Analysis
10861122
- Redundancy method and apparatus for shader column repair
Published: 2020-12-08
This patent protects a system for rendering calculations that includes a shader pipe array with redundancy features, enabling the identification of defective shader pipes and the independent rerouting of data to a redundant shader pipe array through horizontal paths, ensuring uninterrupted rendering performance.
C
Breadth
B
Complexity
C
Enforceability
Claims
Infringement Analysis
10324860
- Memory heaps in a memory model for a unified computing system
Published: 2019-06-18
The patent describes a method and system for managing memory allocation in a multi-processor environment by mapping shared memory addresses to multiple virtual memory pools, thereby allowing fine control over accessibility and resource management for each processor.
C
Breadth
B
Complexity
C
Enforceability
Claims
Infringement Analysis
10205956
- Texture compression techniques
Published: 2019-02-12
This patent protects a method and system for texture compression that involves variable partitioning of pixels into subsets, selective compression based on quality thresholds, and techniques such as palletization and color ramp definitions, enabling efficient storage and representation of textures.
B
Breadth
C
Complexity
C
Enforceability
Claims
Infringement Analysis